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HUF76145P3, HUF76145S3S
Data Sheet December 2001
75A, 30V, 0.0045 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs
These N-Channel power MOSFETs are manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products. Formerly developmental type TA76145.
Features
* Logic Level Gate Drive * 75A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.0045 * Temperature Compensating PSPICE(R) Model * Temperature Compensating SABERTM Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER HUF76145P3 HUF76145S3S PACKAGE TO-220AB TO-263AB BRAND 76145P 76145S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF76145S3ST.
Symbol
D
JEDEC TO-263AB
G
S
GATE SOURCE
DRAIN (FLANGE)
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 16 75 75 75 Figure 4 Figure 6 270 2.17 -40 to 150 300 260 W W/oC
oC oC oC
V V V A A A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC
30 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance
IGSS
VGS = 16V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 11) ID = 75A, VGS = 10V (Figures 9, 10) ID = 75A, VGS = 5V (Figure 9) ID = 75A, VGS = 4.5V (Figure 9)
1 -
0.0035 0.0043 0.0046
3 0.0045 0.0058 0.0065
V
THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 75A, RL = 0.20, VGS = 4.5V, RGS = 2.5 (Figure 15) 26 145 35 39 255 110 ns ns ns ns ns ns RJC RJA (Figure 3) TO-220 and TO-263 0.46 62
oC/W oC/W
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S
Electrical Specifications
PARAMETER TA = 25oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 4900 2520 560 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID 75A, RL = 0.20 Ig(REF) = 1.0mA (Figure 14) 130 73 4.65 12.30 40.00 156 88 5.6 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 75A, RL = 0.20, VGS = 10V, RGS = 2.2 (Figure 16) 16 57 53 38 110 135 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 75A ISD = 75A, dISD/dt = 100A/s ISD = 75A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 115 255 UNITS V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 60 VGS = 4.5V 40 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 80 VGS = 10V
20
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S Typical Performance Curves
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 SINGLE PULSE 0.01 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
(Continued)
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
5000
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
1000
I = I25
175 - TC 150
VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 VGS = 5V
100
50 10-5
10-3
10-2 t, PULSE WIDTH (s)
10-1
100
101
FIGURE 4. PEAK CURRENT CAPABILITY
1000 1000 IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100s 100 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 10 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
100
STARTING TJ = 25oC STARTING TJ = 150oC
1ms
10ms 100 10 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S Typical Performance Curves
150
(Continued)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A)
150 VGS = 10V VGS = 5V VGS = 4.5V 90 VGS = 4V 60 VGS = 3V VGS = 3.5V
ID, DRAIN CURRENT (A)
120
120
90
60 150oC 30 -40oC 25oC 0 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V)
30
VDD = 15V 0 0 1 2
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 3 4
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
20 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 75A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 15 ID = 50A 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 75A 1.5
1.2
5 ID = 25A
0.9
0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V)
0.6 -60
0
60
120
180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.4 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.2
1.2 ID = 250A
1.1
1.0
0.8
1.0
0.6
0.4 -60
0
60
120
180
0.9 -60
TJ, JUNCTION TEMPERATURE (oC)
0 60 120 TJ , JUNCTION TEMPERATURE (oC)
180
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S Typical Performance Curves
8000 VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS 4000 COSS 2000 CRSS 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
(Continued)
10
C, CAPACITANCE (pF)
6000
8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 50A ID = 25A 80 Qg , GATE CHARGE (nC) 120 160
2 VDD = 15V 0 0 40
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
1200 VGS = 4.5V, VDD = 15V, ID = 75A, RL= 0.20 1000 SWITCHING TIME (ns) 800 td(OFF) 600 400 200 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () tr
1000 VGS = 10V, V DD = 15V, ID = 75A, RL= 0.20 800 SWITCHING TIME (ns) td(OFF) 600 tf 400 tr 200 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () tf
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
-
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S Test Circuits and Waveforms
(Continued)
VDS RL VDD VDS VGS = 10 VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S PSPICE Electrical Model
SUBCKT HUF76145 2 1 3 ;
CA 12 8 7.75e-9 CB 15 14 7.45e-9 CIN 6 8 4.47e-9
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RLDRAIN DBREAK 11 + 17 EBREAK 18 5 DRAIN 2
rev 6 Apr98
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 33.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 2.60e-9 LSOURCE 3 7 1.10e-9 KGATE LSOURCE LGATE 0.0085 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
S1A GATE 1 RLGATE
RSLC2
5 51
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S2A RBREAK 17 18 RVTEMP CB + 6 8 EDS 5 8 14 IT 19 7 SOURCE 3
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 0.59e-3 RGATE 9 20 0.898 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.20e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
12 S1B CA
13 8 13
14 13 S2B +
15
EGS
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*750),3))} .MODEL DBODYMOD D (IS = 6.01e-12 IKF = 20 RS = 1. 72e-3 TRS1 = 1.01e-3 TRS2 = 1.21e-6 CJO = 8.41e-9 TT = 4.84e-8 M = 0.45 ) .MODEL DBREAKMOD D (RS = 6.80e- 2TRS1 = 1.12e- 3TRS2 = 1.25e-6 ) .MODEL DPLCAPMOD D (CJO = 4.25e- 9IS = 1e-3 0N = 10 M = 0.61) .MODEL MMEDMOD NMOS (VTO = 1.74 KP = 5.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.898) .MODEL MSTROMOD NMOS (VTO = 2.10 KP = 245 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.98 RS= 0.1) .MODEL RBREAKMOD RES (TC1 = 1.01e- 3TC2 = 1.07e-7) .MODEL RDRAINMOD RES (TC1 = 1.58e-2 TC2 = 3.76e-5) .MODEL RSLCMOD RES (TC1 = 1.02e-4 TC2 = -1.13e-4) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.73e-3 TC2 = -1.01e-5) .MODEL RVTEMPMOD RES (TC1 = -1.50e- 3TC2 = 1.25e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.00 VOFF= -1.50) VON = -1.50 VOFF= -6.00) VON = 0.00 VOFF= 0.45) VON = 0.45 VOFF= 0.00)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
-
RDRAIN 21 16
DBODY
MWEAK MMED
VBAT +
8 22 RVTHRES
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S SABER Electrical Model
REV 6 Apr 1998 template huf76145 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 6.01e-12, cjo = 8.41e-9, tt = 4.84e-8, m = 0.45) d..model dbreakmod = () d..model dplcapmod = (cjo = 4.25e-9, is = 1e-30, n = 10, m = 0.61) m..model mmedmod = (type=_n, vto = 1.74, kp = 5.00, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.10, kp = 245, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.48, kp = 0.10, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -1.5) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = -6.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = 0.45) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.45, voff = 0.0) c.ca n12 n8 = 7.75e-9 c.cb n15 n14 = 7.45e-9 c.cin n6 n8 = 4.47e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod
LGATE ESG + GATE 1 EVTEMP RGATE + 18 22 9 20
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK DBODY MMED MSTRO CIN 8 EBREAK + 17 18 71 RDBODY 5 DRAIN 2
6 8 EVTHRES + 19 8 6
50 RDRAIN 21 16
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9 RLGATE l.lgate n1 n9 = 2.60e-9 l.lsource n3 n7 = 1.10e-9 k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.01e-3, tc2 = 1.07e-7 res.rdbody n71 n5 = 1.72e-3, tc1 = 1.01e-3, tc2 = 1.21e-6 res.rdbreak n72 n5 = 6.80e-2, tc1 = 1.12e-3, tc2 = 1.25e-6 res.rdrain n50 n16 = 0.59e-3, tc1 = 1.58e-2, tc2 = 3.76e-5 res.rgate n9 n20 = 0.898 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 1.02e-4, tc2 = -1.13e-4 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.20e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.50e-3, tc2 = 1.25e-6 res.rvthres n22 n8 = 1, tc1 = -2.73e-3, tc2 = -1.01e-5 spe.ebreak n11 n7 n17 n18 = 33.50 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1
RSOURCE
LSOURCE 7 RLSOURCE SOURCE 3
S1A 12 13 8 13 + EGS 6 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
RBREAK 18 RVTEMP 19
S1B CA
VBAT +
-
-
8 22 RVTHRES
equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/750))** 3)) } }
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
HUF76145P3, HUF76145S3S SPICE Thermal Model
REV Aug 2000 HUF76145T CTHERM1 th 6 6.3e-3 CTHERM2 6 5 1.5e-2 CTHERM3 5 4 2.0e-2 CTHERM4 4 3 3.0e-2 CTHERM5 3 2 8.0e-2 CTHERM6 2 tl 1.5e-1 RTHERM1 th 6 5.0e-3 RTHERM2 6 5 1.8e-2 RTHERM3 5 4 5.0e-2 RTHERM4 4 3 8.5e-2 RTHERM5 3 2 1.0e-1 RTHERM6 2 tl 1.1e-1
th JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model HUF76145T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.3e-3 ctherm.ctherm2 6 5 = 1.5e-2 ctherm.ctherm3 5 4 = 2.0e-2 ctherm.ctherm4 4 3 = 3.0e-2 ctherm.ctherm5 3 2 = 8.0e-2 ctherm.ctherm6 2 tl = 1.5e-1 rtherm.rtherm1 th 6 = 5.0e-3 rtherm.rtherm2 6 5 = 1.8e-2 rtherm.rtherm3 5 4 = 5.0e-2 rtherm.rtherm4 4 3 = 8.5e-2 rtherm.rtherm5 3 2 = 1.0e-1 rtherm.rtherm6 2 tl = 1.1e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2001 Fairchild Semiconductor Corporation
HUF76145P3, HUF76145S3S Rev. B
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FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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